ZX Breakout

This is a CPLD (complex programmable logic device) breakout board for the Spectrum (including 128K and Amstrad models). The original idea behind this board was to provide a breakout board for the ZX Spectrum bus signals, and also level shifting of all the signals to 3.3v with a second set of breakout pins. This was to provide an interface to chips that are not 5v tolerant, such as all current in-production FPGAs.

Using a CPLD instead of simple level shifters does two things: it provides the original functionality of a breakout board with a level shifter since a 3.3v CPLD with 5v tolerant IO can be used for this purpose, and for prototyping or making the logic for other things too - in other words, make a versatile breakout board for both the ZX bus and a CPLD.

Either the Xilinx XC9572XL or the XC95144XL CPLD can be used on this board. To give a rough idea of the logic resources these CPLDs provide, Chris Smith's timing accurate ULA replacement fills an XC95144XL, that's to say this CPLD has a similiar amount of resource to the Spectrum ULA.

The board

ZX Breakout PCB

The PCB features the following:

• All major ZX bus digital signals routed to the CPLD.
• Header for ZX signals, nearest the Spectrum edge connector.
• 3.3v linear power supply for the CPLD.
• JTAG header for programming the CPLD.
• Ability to control the ROMCS line.
• Clock is inverted (to be in phase with the CPU clock) by a Schmitt-trigger buffer giving sharper rising and falling edges.
• Two headers for CPLD signals - a 40 pin header with 32 CPLD general purpose IOs, and a 10 pin header with 7 general purpose IOs.
• 40 pin header laid out with ground and power pins in the same location as an IDE connector.
• 4 layer PCB with solid ground and power planes for ideal CPLD performance.

Additionally, the ZX signals and CPLD pin locations are shown in the silk screen, so you know what you're connecting to without having to reach for a datasheet.

Pin locations

ZX bus to CPLD

ZX bus function to CPLD function block mapping is optimized for the XC9572, being the smallest device with fewest resources. For the '72, the data bus and upper half of the address bus is grouped into function block 1, and the lower half of the address bus and control signals in function block 3. The remaining pins go to the GPIO headers.

The ZX clock is mapped to a global clock signal, and the reset signal is inverted and buffered and routed to the global system reset pin. A global clock signal is available on the GPIO header.

ZX signal	CPLD pin	XC9572 FB	XC95144 FB	Comments
D0	18	1	1
D1	20	1	1
D2	22	1	1
D3	29	1	3
D4	30	1	3
D5	28	1	3
D6	25	1	3
D7	17	1	1
A0	32	3	3
A1	35	3	5
A2	37	3	5
A3	41	3	5
A4	59	3	7
A5	58	3	7
A6	56	3	7
A7	55	3	7
A8	40	1	5
A9	39	1	5
A10	36	1	5
A11	33	1	3
A12	15	1	1
A13	16	1	1
A14	13	1	1
A15	14	1	1
/MREQ	50	3	7
/IORQ	52	3	7
/RD	53	3	7
/WR	54	3	7
/M1	60	3	7
/INT	42	3	5
/NMI	49	3	5
CLK	23	1	5	Buffered; CPLD GCK2
RESET	99	2	3	Buffered; CPLD GSR (active high)

40 pin header

The 40 pin header is numbered using the ribbon cable style of numbering. Pin 1 is at the top right hand side of the connector, when looking down at the component side of the PCB, with the ZX edge connector at the bottom (in other words, as shown in the image on this page).

Header pin	CPLD pin	XC9572 FB	XC95144 FB	Comments
1	4
2	GND
3	71	4
4	40	4
5	74	4
6	72	4
7	77	4
8	76	4
9	79	4
10	78	4
11	82	4
12	81	4
13	86	4
14	85	4
15	89	4
16	87	2
17	91	2
18	90	4
19	GND
20	3.3v
21	92	2
22	GND
23	93	2
24	GND
25	94	2
26	GND
27	95	2
28	96	2
29	97	2
30	GND
31	1	2
32	3	2		GTS1
33	4	2		GTS2
34	6	2
35	8	2
36	9	2
37	10	2
38	11	2
39	12	2
40	GND