ZX SPI - Revision history

Winston at 21:34, 25 June 2013

2013-06-25T21:34:39Z

← Older revision		Revision as of 22:34, 25 June 2013
Line 10:		Line 10:

	''Caveats:''		''Caveats:''
	I've not done a great deal of Verilog, so it's likely the implementation can be made a bit more efficient. In particular, the parallel to serial and serial to parallel shift registers are double buffered, it's the easiest way of separating the two clock domains (Z80 clock and SPI clock domains), but it's probably possible to do something more convoluted that uses fewer flip flops~~. I've also not had the opportunity to test SPI reads on real hardware, only on the ISE simulator. It should work, but I need to get an SPI device that can be read from to test it~~.		I've not done a great deal of Verilog, so it's likely the implementation can be made a bit more efficient. In particular, the parallel to serial and serial to parallel shift registers are double buffered, it's the easiest way of separating the two clock domains (Z80 clock and SPI clock domains), but it's probably possible to do something more convoluted that uses fewer flip flops.

	The Verilog code and Xilinx ISE project file can be obtained [http://spectrum.alioth.net/svn/listing.php?repname=ZXSPI&path=%2Ftrunk%2Fise%2F#path_trunk_ise_ here, from WebSVN]		The Verilog code and Xilinx ISE project file can be obtained [http://spectrum.alioth.net/svn/listing.php?repname=ZXSPI&path=%2Ftrunk%2Fise%2F#path_trunk_ise_ here, from WebSVN]

			There's a demonstration of it in action on YouTube here: [https://www.youtube.com/watch?v=ptBa7qrxDao ZX SPI and Nixie display]

	== Using ZXSPI ==		== Using ZXSPI ==

Winston: /* The control and status register */

2013-06-20T23:00:46Z

The control and status register

← Older revision		Revision as of 00:00, 21 June 2013
Line 28:		Line 28:
	bit 6-5 - SPI chip select to use		bit 6-5 - SPI chip select to use
	bit 4 - 1 = use clock divider, 0 = don't use clock divider		bit 4 - 1 = use clock divider, 0 = don't use clock divider
	bit 3-1 - set clock speed		bit 3-1 - set clock speed (bit 4 must be set to 1 to use this)
	bit 0 - select clock polarity (0 = CPOL 0, 1 = CPOL 1)		bit 0 - select clock polarity (0 = CPOL 0, 1 = CPOL 1)

Winston: /* The control and status register */

2013-06-20T23:00:13Z

The control and status register

← Older revision		Revision as of 00:00, 21 June 2013
Line 31:		Line 31:
	bit 0 - select clock polarity (0 = CPOL 0, 1 = CPOL 1)		bit 0 - select clock polarity (0 = CPOL 0, 1 = CPOL 1)

	After the Spectrum is powered up or reset, the defaults are: Clock speed 1.~~75MHz~~, CPOL 0, using chip select 1.		After the Spectrum is powered up or reset, the defaults are: Clock speed 3.5MHz, CPOL 0, using chip select 1.

	When reading from the register, the following bits are defined:		When reading from the register, the following bits are defined:

Winston: /* Speed of INI/OUTI versus SPI operations */

2013-06-20T20:07:59Z

Speed of INI/OUTI versus SPI operations

← Older revision		Revision as of 21:07, 20 June 2013
Line 102:		Line 102:

	At lower speeds you'll either need to calculate how many T-states it'll take to complete the SPI operation, and see if your code takes longer than this in between subsequent I/O operations. In the case of a slow SPI serial clock, for a machine code program you'll probably need to check the contents of bit 7 of the status register (0x053B) before starting a new I/O operation.		At lower speeds you'll either need to calculate how many T-states it'll take to complete the SPI operation, and see if your code takes longer than this in between subsequent I/O operations. In the case of a slow SPI serial clock, for a machine code program you'll probably need to check the contents of bit 7 of the status register (0x053B) before starting a new I/O operation.

			You can ignore contention - except on a +3 or +2A/B - because the serial clock is directly derived from the CPU clock, and so while the CPU clock is halted during contention periods, then so will the serial clock. However, this is not the case on a +3 or +2A/B since the CPU clock keeps running and contention is achieved by other means. So for these machines you'll need to use uncontended memory if you want your T-state calculations versus SPI operation calculations accurate.

	== Default pins ==		== Default pins ==

Winston: /* Setting SPI clock speed */

2013-06-20T20:03:04Z

Setting SPI clock speed

← Older revision		Revision as of 21:03, 20 June 2013
Line 46:		Line 46:

	When bit 4 is set to 1:		When bit 4 is set to 1:

	Bits 3-1 Speed		Bits 3-1 Speed
	0 1.75MHz		0 1.75MHz

Winston: /* Setting SPI clock speed */

2013-06-20T20:02:57Z

Setting SPI clock speed

← Older revision		Revision as of 21:02, 20 June 2013
Line 44:		Line 44:

	Bits 4-1 of the control register (0x053B) set the SPI serial clock speed. If bit 4 is set to 0, then the clock divider is bypassed and the 3.5MHz CPU clock is used as the SPI serial clock. Otherwise, if bit 4 is set to 1, the serial clock speed is determined by a simple 8 stage clock divider. The fastest speed (1.75MHz) is basically the Z80 clock divided by two. Here's a table of the speeds selectable when bit 4 is set:		Bits 4-1 of the control register (0x053B) set the SPI serial clock speed. If bit 4 is set to 0, then the clock divider is bypassed and the 3.5MHz CPU clock is used as the SPI serial clock. Otherwise, if bit 4 is set to 1, the serial clock speed is determined by a simple 8 stage clock divider. The fastest speed (1.75MHz) is basically the Z80 clock divided by two. Here's a table of the speeds selectable when bit 4 is set:

			When bit 4 is set to 1:

	Bits 3-1 Speed		Bits 3-1 Speed

Winston at 20:02, 20 June 2013

2013-06-20T20:02:29Z

← Older revision		Revision as of 21:02, 20 June 2013
Line 76:		Line 76:

	The same comments about multiple writes in the above section (checking the control register's bit 7) applies to reading too, since they are effectively the same operation.		The same comments about multiple writes in the above section (checking the control register's bit 7) applies to reading too, since they are effectively the same operation.

			=== Speed of INI/OUTI versus SPI operations ===

			The SPI read/write operation starts on the next rising clock edge (don't forget that the edge connector CLK signal is inverted with respect to the clock the CPU sees) after the IO write completes. The I/O operation is performed on the 4th M cycle of an INI or OTI instruction. The fastest possible read and write you will be able to do is something like this:

			ld bc, 0x053B ; B must be 1 greater than I/O port
			ld hl, ptr
			outi ; write (hl) to port 0x043B
			inc b ; SPI write will begin during execution of this instruction
			outi
			inc b
			outi
			...

			The SPI operation takes 8 T-states to complete at full speed, since one bit is read/written to MOSI and MISO per T-stat. This starts on the next rising edge of the internal SPI clock, which will be halfway through the first T-state of INC B. Therefore the SPI operation is guaranteed to have completed before the next OUTI writes to the device. The INC B and first 3 M-cycles of OUTI will require 16 T-states to complete, and the IORQ line doesn't go low until the 17th T-state. This will mean that a 1.75MHz serial clock should be usable in the code above. In this case:

			ld bc, 0x043B
			out (c), a
			out (c), d
			out (c), e

			only the 3.5MHz serial clock is fast enough for the SPI operation to complete before the next OUT. The OUT (C), r instruction has 3 M-cycles, each 4 T-states long, so there will be 9 T-states from IORQ going high until the next OUT operation beginning.

			At lower speeds you'll either need to calculate how many T-states it'll take to complete the SPI operation, and see if your code takes longer than this in between subsequent I/O operations. In the case of a slow SPI serial clock, for a machine code program you'll probably need to check the contents of bit 7 of the status register (0x053B) before starting a new I/O operation.

	== Default pins ==		== Default pins ==

Winston at 19:41, 20 June 2013

2013-06-20T19:41:43Z

← Older revision		Revision as of 20:41, 20 June 2013
Line 2:		Line 2:

	''Features:''		''Features:''
	* SPI clock from 1.~~75MHz~~ to ~~some absurdly low frequency (up to 16 stages of division, that would make 26 hertz!)~~		* SPI clock from 3.5MHz to 14kHz
	* Supports CPOL 0 (normal clock polarity) and CPOL 1 (inverted clock polarity)		* Supports CPOL 0 (normal clock polarity) and CPOL 1 (inverted clock polarity)
	* Full duplex		* Full duplex
			* Four chip selects
	* Synchronous design that should work fine with an FPGA		* Synchronous design that should work fine with an FPGA
	* Requires 70 macrocells (fits an XC9572)		* Requires 62 macrocells (fits an XC9572)

	''Caveats:''		''Caveats:''
Line 26:		Line 27:
	bit 7 - not used		bit 7 - not used
	bit 6-5 - SPI chip select to use		bit 6-5 - SPI chip select to use
	bit 4-1 - set clock speed		bit 4 - 1 = use clock divider, 0 = don't use clock divider
			bit 3-1 - set clock speed
	bit 0 - select clock polarity (0 = CPOL 0, 1 = CPOL 1)		bit 0 - select clock polarity (0 = CPOL 0, 1 = CPOL 1)

Line 35:		Line 37:
	bit 7 - 1 = Busy, 0 = Ready for a new read/write operation		bit 7 - 1 = Busy, 0 = Ready for a new read/write operation
	bit 6-5 - SPI chip select in use		bit 6-5 - SPI chip select in use
	bit 4-1 - Current clock speed		bit 4 - 1 = using clock divider, 0 = not using clock divider
			bit 3-1 - Current clock speed
	bit 0 - Current clock polarity		bit 0 - Current clock polarity

	=== Setting SPI clock speed ===		=== Setting SPI clock speed ===

	Bits 4-1 of the control register (0x053B) set the SPI clock speed. ~~The~~ clock speed is determined by a simple 16 stage clock divider. The fastest speed (1.75MHz) is basically the Z80 clock divided by ~~two. So to determine the amount that the 1.75MHz clock is divided by, take the value (0 to 15) and raise to the power of~~ two. Here is a table of the ~~most useful clock~~ speeds:		Bits 4-1 of the control register (0x053B) set the SPI serial clock speed. If bit 4 is set to 0, then the clock divider is bypassed and the 3.5MHz CPU clock is used as the SPI serial clock. Otherwise, if bit 4 is set to 1, the serial clock speed is determined by a simple 8 stage clock divider. The fastest speed (1.75MHz) is basically the Z80 clock divided by two. Here's a table of the speeds selectable when bit 4 is set:

	Bits 4-1 Speed		Bits 3-1 Speed
	0 1.75MHz		0 1.75MHz
	1 875kHz		1 875kHz
Line 51:		Line 54:
	6 27kHz		6 27kHz
	7 14kHz		7 14kHz
	~~8 7kHz~~
	~~9 3.5kHz~~

	~~The ludicrously low speeds when the divider is set from 10 to 15 may be helpful while debugging, but probably not for actually running an SPI device!~~

	=== Chip selects ===		=== Chip selects ===

Winston: /* The control and status register */

2013-06-19T21:16:59Z

The control and status register

← Older revision		Revision as of 22:16, 19 June 2013
Line 30:		Line 30:

	After the Spectrum is powered up or reset, the defaults are: Clock speed 1.75MHz, CPOL 0, using chip select 1.		After the Spectrum is powered up or reset, the defaults are: Clock speed 1.75MHz, CPOL 0, using chip select 1.

	If bit 5 is set to 1 when writing to the register, all other bits are ignored. This is to save the trouble of having to read the port back, merge in bit 5 and send it again (or storing the settings in memory).

	When reading from the register, the following bits are defined:		When reading from the register, the following bits are defined:

Winston: /* The control and status register */

2013-06-19T21:16:43Z

The control and status register

← Older revision		Revision as of 22:16, 19 June 2013
Line 29:		Line 29:
	bit 0 - select clock polarity (0 = CPOL 0, 1 = CPOL 1)		bit 0 - select clock polarity (0 = CPOL 0, 1 = CPOL 1)

	After the Spectrum is powered up or reset, the defaults are: Clock speed 1.75MHz, CPOL 0.		After the Spectrum is powered up or reset, the defaults are: Clock speed 1.75MHz, CPOL 0, using chip select 1.

	If bit 5 is set to 1 when writing to the register, all other bits are ignored. This is to save the trouble of having to read the port back, merge in bit 5 and send it again (or storing the settings in memory).		If bit 5 is set to 1 when writing to the register, all other bits are ignored. This is to save the trouble of having to read the port back, merge in bit 5 and send it again (or storing the settings in memory).