Spectranet CPLD - Revision history

Winston at 20:05, 11 July 2010

2010-07-11T20:05:56Z

← Older revision		Revision as of 21:05, 11 July 2010
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	* Bit 2 - Reserved.		* Bit 2 - Reserved.
	* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port 0x023B.		* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port 0x023B.
	* Bit 4-7 - Reserved~~. Set these to the same value as is read back in case they have a use in the future~~.		* Bit 4 - Reserved.
			* Bit 5 - Deny downstream A15 (set to 1 to prevent peripherals from ever seeing /MREQ + A15 low
			* Bit 6, 7 - Reserved.

	On power up, bits 0 and 3 are reset.		On power up, bits 0 and 3 are reset.
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	* BIt 0,1,2 - The current border colour		* BIt 0,1,2 - The current border colour
	* Bit 3 - Programmable trap enable - set to 1 if the programmable trap is enabled.		* Bit 3 - Programmable trap enable - set to 1 if the programmable trap is enabled.
	* Bit 4-7 - Reserved		* Bit 4 - State of 128K screen memory page
			* Bit 5 - Deny downstream A15
			* Bit 6 - W5100 interrupt pin state
			* Bit 7 - Reserved

	The CPLD monitors the border colour sent to port 0xFE so that snapshots of the machine state can be made which have the correct border colour. The border colour can't actually be read from the base Spectrum hardware (except when running BASIC).		The CPLD monitors the border colour sent to port 0xFE so that snapshots of the machine state can be made which have the correct border colour. The border colour can't actually be read from the base Spectrum hardware (except when running BASIC).

	[[Category:Spectranet]]		[[Category:Spectranet]]

Winston at 22:09, 28 June 2010

2010-06-28T22:09:38Z

Winston at 19:27, 27 June 2010

2010-06-27T19:27:19Z

Winston: /* Control and Status Register */

2009-11-05T21:30:11Z

Control and Status Register

← Older revision		Revision as of 22:30, 5 November 2009
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	This register is read/write, and can be accessed on port 0x80EF. Programs can read this register to discover information about the CPLD's state, and to enable or disable a function. At present, 4 bits are used, and the remainder have no effect when written, and when read, return a value of 1. When modifying writeable flags in this register, the result must be merged into the exsting value of the register to prevent undesirable effects, so any program that writes the register, should read it first and only change the bits that need to be changed.		This register is read/write, and can be accessed on port 0x80EF. Programs can read this register to discover information about the CPLD's state, and to enable or disable a function. At present, 4 bits are used, and the remainder have no effect when written, and when read, return a value of 1. When modifying writeable flags in this register, the result must be merged into the exsting value of the register to prevent undesirable effects, so any program that writes the register, should read it first and only change the bits that need to be changed.

	The bits are defined as follows:		The bits are defined as follows. When writing to the port:

	* Bit 0 - Page-in bit: set to 1, this causes the Spectranet memory to be paged in.		* Bit 0 - Page-in bit: set to 1, this causes the Spectranet memory to be paged in.
	* Bit 1 - ~~Execution trap (Read only) Set to 1 if an execution trap is currently active~~.		* Bit 1 - Reserved.
	* Bit 2 - ~~Call trap (Read only) Set to 1 if a call trap is currently active~~.		* Bit 2 - Reserved.
	* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port 0x80ED.		* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port 0x80ED.
	* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.		* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.

	On power up ~~or reset~~, bits 0 to 3 are ~~set to 0, and 4-7 are set to 1~~.		On power up, bits 0 and 3 are reset.

	Bit 1 ~~will be set whenever address 0x0008 (RST8) or 0x0066 (NMI) are trapped by~~ the ~~CPLD. They remain set until the ROM~~ is ~~paged out (either by resetting bit 0 or by the page out trap at 0x007C)~~. Bit ~~2 is set if a CALL instruction is encountered, calling addresses 0x3FF8~~-~~0x3FFF~~. ~~This also remains set until~~ the ~~ROM is paged out~~.		When reading from the port:
			* BIt 0,1,2 - The current border colour
			* Bit 3 - Programmable trap enable - set to 1 if the programmable trap is enabled.
			* Bit 4-7 - Reserved

			The CPLD monitors the border colour sent to port 0xFE so that snapshots of the machine state can be made which have the correct border colour. The border colour can't actually be read from the base Spectrum hardware (except when running BASIC).

	[[Category:Spectranet]]		[[Category:Spectranet]]

Winston at 13:33, 19 July 2008

2008-07-19T13:33:57Z

← Older revision		Revision as of 14:33, 19 July 2008
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	* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.		* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.

			On power up or reset, bits 0 to 3 are set to 0, and 4-7 are set to 1.

			Bit 1 will be set whenever address 0x0008 (RST8) or 0x0066 (NMI) are trapped by the CPLD. They remain set until the ROM is paged out (either by resetting bit 0 or by the page out trap at 0x007C). Bit 2 is set if a CALL instruction is encountered, calling addresses 0x3FF8-0x3FFF. This also remains set until the ROM is paged out.

	[[Category:Spectranet]]		[[Category:Spectranet]]

Winston at 13:30, 19 July 2008

2008-07-19T13:30:55Z

← Older revision		Revision as of 14:30, 19 July 2008
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	* Bit 2 - Call trap (Read only) Set to 1 if a call trap is currently active.		* Bit 2 - Call trap (Read only) Set to 1 if a call trap is currently active.
	* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port 0x80ED.		* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port 0x80ED.
			* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.


	[[Category:Spectranet]]		[[Category:Spectranet]]

Winston at 13:29, 19 July 2008

2008-07-19T13:29:47Z

@@ Line 49: / Line 49: @@
 * 0x0000 - Conditionally, only on a reset condition.
 * 0x0008 - Conditionally, if the RST8EN jumper is closed.
-* 0x0038 - Conditionally, if interrupt acceptance is enabled and the W5100 has raised an interrupt.
+* 0x0066 - Conditionally, only when the NMI button is pressed on our board, or an NMI is fired by the programmable trap.
 Page-ins are triggered when the following instruction is decoded:
@@ Line 75: / Line 74: @@
 When the Spectranet's NMI switch is closed, the NMI event flip flop is set, and the CPLD generates an NMI signal on the Z80's NMI pin via the Spectrum's edge connector. If the event flip flop is set, and execution is detected at address 0x0066 (the NMI vector) a page in by the normal execution trapper method occurs. The NMI flip flop remains set until the CPLD decodes the RETN (ED 45) instruction on the data bus. The NMI event flip flop remains set until RETN (rather than a page out at 0x007C) so that page-outs can occur as part of the NMI handler (for example, to call the Spectrum's BASIC ROM) without causing multiple NMI signals from being sent.
 [[Category:Spectranet]]

Winston at 21:23, 3 June 2008

2008-06-03T21:23:55Z

← Older revision		Revision as of 22:23, 3 June 2008
Line 69:		Line 69:

	If the page out address is detected with M1 and MREQ active, on the rising edge of M1, the page-in latch is reset, A15OUT reverts to pass through the A15 signal, and HLDROMCS becomes inactive.		If the page out address is detected with M1 and MREQ active, on the rising edge of M1, the page-in latch is reset, A15OUT reverts to pass through the A15 signal, and HLDROMCS becomes inactive.

			=== Non maskable interrupt behaviour ===

			The CPLD only responds to an NMI signal generated by the Spectranet's NMI switch; NMIs from downstream devices are passed on unmolested, and the execution of the Z80's NMI vector are not trapped.

			When the Spectranet's NMI switch is closed, the NMI event flip flop is set, and the CPLD generates an NMI signal on the Z80's NMI pin via the Spectrum's edge connector. If the event flip flop is set, and execution is detected at address 0x0066 (the NMI vector) a page in by the normal execution trapper method occurs. The NMI flip flop remains set until the CPLD decodes the RETN (ED 45) instruction on the data bus. The NMI event flip flop remains set until RETN (rather than a page out at 0x007C) so that page-outs can occur as part of the NMI handler (for example, to call the Spectrum's BASIC ROM) without causing multiple NMI signals from being sent.

	[[Category:Spectranet]]		[[Category:Spectranet]]

Winston at 15:23, 23 December 2007

2007-12-23T15:23:41Z

← Older revision		Revision as of 16:23, 23 December 2007
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	=== Execution trapper - page-ins ===		=== Execution trapper - page-ins ===

	[[Image:Traptiming.png\|thumb\|~~right~~\|400px\|A15OUT and HLDROMCS are activated as soon as M1 + address of interest is seen, but only latched on the falling edge of MREQ.]]		In the following diagram, M1 and MREQ from the CPU is active low. CS from the CPLD is active low, and HLDROMCS is active high.

			<table>
			<tr>
			<td>
			[[Image:Traptiming.png\|thumb\|left\|400px\|A15OUT and HLDROMCS are activated as soon as M1 + address of interest is seen, but only latched on the falling edge of MREQ.]]
			[[Image:Traptiming-glitch.png\|thumb\|right\|400px\|In the case of a 'glitch' due to the bus not being stable before MREQ, page-in signals are briefly active - however, this is unimportant since the glitch will be gone by the falling edge of MREQ, and memories are only active after MREQ.]]
			</td>
			</tr>
			</table>

	The execution trapper pages in when an instruction fetch is detected to the following addresses:		The execution trapper pages in when an instruction fetch is detected to the following addresses:
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	=== Execution trapper - page-outs ===		=== Execution trapper - page-outs ===

			[[Image:Traptiming-unlatch.png\|thumb\|400px\|right\|Our paged ROM state is unlatched on the trailing edge of the M1 cycle for execution at the address 0x007C.]]

	Unlike the page-in, pageouts are performed at the tail end of the M1 cycle. Page outs occur on the following execution addresses:		Unlike the page-in, pageouts are performed at the tail end of the M1 cycle. Page outs occur on the following execution addresses:

Winston at 18:31, 22 December 2007

2007-12-22T18:31:28Z

← Older revision		Revision as of 19:31, 22 December 2007
Line 33:		Line 33:

	=== Execution trapper - page-ins ===		=== Execution trapper - page-ins ===

			[[Image:Traptiming.png\|thumb\|right\|400px\|A15OUT and HLDROMCS are activated as soon as M1 + address of interest is seen, but only latched on the falling edge of MREQ.]]

	The execution trapper pages in when an instruction fetch is detected to the following addresses:		The execution trapper pages in when an instruction fetch is detected to the following addresses:

← Older revision		Revision as of 23:09, 28 June 2010
Line 79:		Line 79:
	A programmable trap is provided, which allows any address in the Z80's address space to cause a trap. It works differently to the fixed traps, in that it doesn't itself cause a ROM page in (since the trap may not be in an area where ROM can be mapped). It instead triggers a non maskable interrupt. The NMI handler is called using the standard behaviour discussed in the last paragraph. System variables are provided to allow the NMI handler to distinguish between an NMI button press and an execution trap NMI. This is documented on the [[Trapping execution]] page.		A programmable trap is provided, which allows any address in the Z80's address space to cause a trap. It works differently to the fixed traps, in that it doesn't itself cause a ROM page in (since the trap may not be in an area where ROM can be mapped). It instead triggers a non maskable interrupt. The NMI handler is called using the standard behaviour discussed in the last paragraph. System variables are provided to allow the NMI handler to distinguish between an NMI button press and an execution trap NMI. This is documented on the [[Trapping execution]] page.

	The execution trap is controlled with a 16 bit value, the little-endian representation of the address to trap. This is sent to the CPLD on port ~~0x02FB~~, using two OUT instructions. The first OUT (~~0x02FB~~),... instruction should contain the LSB of the address, and the second OUT (~~0x02FB~~) instruction should contain the MSB.		The execution trap is controlled with a 16 bit value, the little-endian representation of the address to trap. This is sent to the CPLD on port 0x023B, using two OUT instructions. The first OUT (0x023B),... instruction should contain the LSB of the address, and the second OUT (0x023B) instruction should contain the MSB.

	To prevent the trap firing when it is not desired, it is enabled and disabled by bit 3 of the control register, which is accessed on port ~~0x03FB~~. The programmable execution trap will only fire when bit 3 of the control register is set to 1.		To prevent the trap firing when it is not desired, it is enabled and disabled by bit 3 of the control register, which is accessed on port 0x033B. The programmable execution trap will only fire when bit 3 of the control register is set to 1.

	The timing for the programmable execution trap is the same as for the fixed traps - the trap will be set on the 'leading edge' of the instruction. The CPU does not respond until the instruction completes, so the program counter (pushed onto the stack) when the CPU responds to the NMI will be the address of the next instruction to be executed after the trap. The NMI logic in the CPLD is set in the same way as when the NMI button is pressed, except the signal remains internal to the CPLD.		The timing for the programmable execution trap is the same as for the fixed traps - the trap will be set on the 'leading edge' of the instruction. The CPU does not respond until the instruction completes, so the program counter (pushed onto the stack) when the CPU responds to the NMI will be the address of the next instruction to be executed after the trap. The NMI logic in the CPLD is set in the same way as when the NMI button is pressed, except the signal remains internal to the CPLD.
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	== Control and Status Register ==		== Control and Status Register ==

	This register is read/write, and can be accessed on port ~~0x03FB~~. Programs can read this register to discover information about the CPLD's state, and to enable or disable a function. At present, 4 bits are used, and the remainder have no effect when written, and when read, return a value of 1. When modifying writeable flags in this register, the result must be merged into the exsting value of the register to prevent undesirable effects, so any program that writes the register, should read it first and only change the bits that need to be changed.		This register is read/write, and can be accessed on port 0x033B. Programs can read this register to discover information about the CPLD's state, and to enable or disable a function. At present, 4 bits are used, and the remainder have no effect when written, and when read, return a value of 1. When modifying writeable flags in this register, the result must be merged into the exsting value of the register to prevent undesirable effects, so any program that writes the register, should read it first and only change the bits that need to be changed.

	The bits are defined as follows. When writing to the port:		The bits are defined as follows. When writing to the port:
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	* Bit 1 - Reserved.		* Bit 1 - Reserved.
	* Bit 2 - Reserved.		* Bit 2 - Reserved.
	* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port ~~0x02FB~~.		* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port 0x023B.
	* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.		* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.

← Older revision		Revision as of 20:27, 27 June 2010
Line 79:		Line 79:
	A programmable trap is provided, which allows any address in the Z80's address space to cause a trap. It works differently to the fixed traps, in that it doesn't itself cause a ROM page in (since the trap may not be in an area where ROM can be mapped). It instead triggers a non maskable interrupt. The NMI handler is called using the standard behaviour discussed in the last paragraph. System variables are provided to allow the NMI handler to distinguish between an NMI button press and an execution trap NMI. This is documented on the [[Trapping execution]] page.		A programmable trap is provided, which allows any address in the Z80's address space to cause a trap. It works differently to the fixed traps, in that it doesn't itself cause a ROM page in (since the trap may not be in an area where ROM can be mapped). It instead triggers a non maskable interrupt. The NMI handler is called using the standard behaviour discussed in the last paragraph. System variables are provided to allow the NMI handler to distinguish between an NMI button press and an execution trap NMI. This is documented on the [[Trapping execution]] page.

	The execution trap is controlled with a 16 bit value, the little-endian representation of the address to trap. This is sent to the CPLD on port ~~0x80ED~~, using two OUT instructions. The first OUT (~~0x80ED~~),... instruction should contain the LSB of the address, and the second OUT (~~0x80ED~~) instruction should contain the MSB.		The execution trap is controlled with a 16 bit value, the little-endian representation of the address to trap. This is sent to the CPLD on port 0x02FB, using two OUT instructions. The first OUT (0x02FB),... instruction should contain the LSB of the address, and the second OUT (0x02FB) instruction should contain the MSB.

	To prevent the trap firing when it is not desired, it is enabled and disabled by bit 3 of the control register, which is accessed on port ~~0x80EF~~. The programmable execution trap will only fire when bit 3 of the control register is set to 1.		To prevent the trap firing when it is not desired, it is enabled and disabled by bit 3 of the control register, which is accessed on port 0x03FB. The programmable execution trap will only fire when bit 3 of the control register is set to 1.

	The timing for the programmable execution trap is the same as for the fixed traps - the trap will be set on the 'leading edge' of the instruction. The CPU does not respond until the instruction completes, so the program counter (pushed onto the stack) when the CPU responds to the NMI will be the address of the next instruction to be executed after the trap. The NMI logic in the CPLD is set in the same way as when the NMI button is pressed, except the signal remains internal to the CPLD.		The timing for the programmable execution trap is the same as for the fixed traps - the trap will be set on the 'leading edge' of the instruction. The CPU does not respond until the instruction completes, so the program counter (pushed onto the stack) when the CPU responds to the NMI will be the address of the next instruction to be executed after the trap. The NMI logic in the CPLD is set in the same way as when the NMI button is pressed, except the signal remains internal to the CPLD.
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	== Control and Status Register ==		== Control and Status Register ==

	This register is read/write, and can be accessed on port ~~0x80EF~~. Programs can read this register to discover information about the CPLD's state, and to enable or disable a function. At present, 4 bits are used, and the remainder have no effect when written, and when read, return a value of 1. When modifying writeable flags in this register, the result must be merged into the exsting value of the register to prevent undesirable effects, so any program that writes the register, should read it first and only change the bits that need to be changed.		This register is read/write, and can be accessed on port 0x03FB. Programs can read this register to discover information about the CPLD's state, and to enable or disable a function. At present, 4 bits are used, and the remainder have no effect when written, and when read, return a value of 1. When modifying writeable flags in this register, the result must be merged into the exsting value of the register to prevent undesirable effects, so any program that writes the register, should read it first and only change the bits that need to be changed.

	The bits are defined as follows. When writing to the port:		The bits are defined as follows. When writing to the port:
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	* Bit 1 - Reserved.		* Bit 1 - Reserved.
	* Bit 2 - Reserved.		* Bit 2 - Reserved.
	* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port ~~0x80ED~~.		* Bit 3 - Programmable trap enable. When set to 1, an NMI is fired whenever the CPU fetches an instruction at the address in the 16-bit register at port 0x02FB.
	* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.		* Bit 4-7 - Reserved. Set these to the same value as is read back in case they have a use in the future.